EPROMs, E.sup.2 PROMs, and Flash E.sup.2 PROMs (hereafter collectively, PROMs) have several structures which allow them to hold a charge without refresh for extended periods of time. FIG. 1 shows a top view of a PROM array, FIG. 2 shows a cross section along "AA" of FIG. 1, and FIG. 3 shows a cross section along "BB" of FIG. 1. The charge itself is stored on a "floating gate" 10 also referred to as Poly 1 or P1, which is a structure of polycrystalline silicon (hereafter, poly) surrounded on all sides by a layer of oxide 12. Located superjacent and parallel to this P1 structure is another poly structure, the "control gate" 14 or P2. P1 10 and P2 14 act as the two plates of a capacitor. Below the P1 layer are two N+ junctions, one which acts as the transistor source 16 and the other as the drain 18, which are doped into a p-type substrate 20. The portion of the substrate 20 between the source 16 and the drain 18 is the channel 22. The cell of FIG. 1 functions like an enhancement-type n-channel metal oxide semiconductor field effect transistor (MOSFET) with two gates of poly.
There are many ways to program a PROM. In one technique, a potential such as for example 12 V, is applied on the control gate. Simultaneously, a voltage pulse, for example 8 V, is applied between source and drain. The large positive voltage on the control gate establishes an electric field in the insulating oxide. This electric field attracts the electrons generated from the so-called "avalanche breakdown" of the transistor due to the high drain and control gate voltages, and accelerates them toward the floating gate, which they enter through the oxide. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped.
To return the floating gate from a charged state to a state with no charge, the electrons are caused to return to the substrate. In an EPROM, this is accomplished with ultraviolet light which excites the electrons past a certain energy state, thereby allowing them to pass through the oxide and return to the substrate. In an E.sup.2 PROM, this excitation is accomplished with an electrical field.
There are structures that make up a PROM array which are common to several transistors in the array. FIG. 1 is a top view of an array showing the transistor sources 16, drains 18, digit lines 24, floating gates 10, and control or "word" lines 26 which form control gates 14 as they pass over the floating gates 10. Also shown as a dotted line is the "active area" 28 interspersed with areas of field oxide 30. A single word line 26 is common to all transistors in a single column acting as a control gate 14 for all transistors in the column. When selected it activates all transistors in the column. The source regions 16, which run parallel with the control lines 26, are common to all transistors in two adjacent columns. Individual transistor drains 18 are common to two transistors in adjacent columns. The digit (or bit) lines 24 are common with the drains 18 of all transistors in a single row.
To read the datum on a floating gate 10, the control line 26 of the cell to be read is activated, for example by bringing it to between 2.5 V and 3.5 V, which causes all transistors in the selected column to become active. The voltage applied to the control gate 26 is above the threshold voltage (V.sub.T) of a cell holding a "1" state, and below the threshold voltage of a cell storing a "0". If a cell is set to a zero, arbitrarily defined by storing -3 V on the floating gate 10, the potential between the control gate 26 and the transistor channel 22 is not high enough to trip the transistor. If a cell is set to a one, arbitrarily defined by storing 0 V on the floating gate 10, the potential between the control gate 26 and the channel 22 is high enough to trip the transistor. After the control gate 26 is activated, each cell along that control gate 26 outputs the cell information on their respective digit lines 24. The information on the digit line 24 which corresponds to the cell to be read is obtained with a sense amplifier (not shown), with one sense amp for each digit line.
Electrons stored on the floating gate can leak to the source, to the drain, or to the control gate thereby causing the floating gate to leak to ground, the floating gate's unprogrammed state. This will cause the transistor to trip accidentally.
Another phenomenon which occurs increasingly as cell sizes decrease and PROMs are made more densely is drain coupling. Drain coupling can occur due to the drain-to-floating-gate capacitance. When a voltage is applied to the drain during a read, for example, the influence of the floating gate on the channel can slightly forward bias the flow of electrons between the source and drain, thereby resulting in an undesired leakage of electrons between the drain and source. This can make it appear that the transistor has tripped, thereby indicating that the cell is not storing a charge when it actually is.
A PROM design which protects against the undesired phenomena listed above would be a desireable structure.
Referring to FIGS. 4 and 5, PROM designs have been used which have a control line 40 which passes over a floating gate 42 which is only a fraction of the length of a conventional PROM cell, for instance half the length of a conventional floating gate. (Note that for purposes of this disclosure, the term "length" indicates a direction of the channel or floating gate perpendicular with the word line, and "width" indicates a direction of the channel or floating gate parallel with the word line.) The floating gate 42 does not extend all the way between the source 16 and drain 18. The cross section along AA of FIG. 4 appears identical to the structure of FIG. 3, while the cross section along BB of FIG. 4 is shown in FIG. 5. In these types of "half-gate" designs, the control line 40 is of conventional size and extends completely across the channel 22. The distance across the control line 40 is therefore twice the distance across the fractional floating gate 42. Cells employing the floating gate 42 of decreased distance between the source 16 and drain 18 are an attempt to solve the over-erase (depletion mode) problem by inserting a conventional transistor as a part of the cell. The region of the cell wherein no floating gate 42 covers the channel 22 acts as the conventional transistor.